1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device, and more particularly to such a method by which it is possible to decrease resistance of a gate electrode and source/drain.
2. Description of the Related Art
These days, a gate electrode tends to be more micro-sized and an impurity diffusion layer or source/drain region tends to have a shallower junction depth in order to improve performance of a CMOS device and so on. Various attempts have been made in the prior art to decrease resistance of a gate electrode and an impurity diffusion layer. One of the prior art methods is to form a film composed of refractory metal or refractory metal silicide on both the gate electrode and impurity diffusion layer.
For instance, Japanese Unexamined Patent Publication No. 3-288443 has suggested a method of forming a sidewall having a higher height than a polysilicon gate electrode to thereby prevent short-circuiting between a gate electrode and source/drain regions. Hereinbelow is explained this prior method with reference to FIGS. 1A to 1G which are cross-sectional views of a semiconductor device, showing respective steps of the method.
First, as illustrated in FIG. 1A, a plurality of field oxides 603 are selectively formed by selective oxidation on a p-type single crystal silicon substrate 601. Then, gate oxides 604 are deposited by thermal oxidation in device formation regions surrounded by the field oxides 603. Then, a polysilicon film 605 is deposited over the field oxides 603 and the gate oxides 604 by low-pressure chemical vapor deposition (LPCVD), followed by diffusion of phosphorus into the polysilicon film 605. Then, a silicon nitride film 607 is deposited over the polysilicon film 605 by low pressure chemical vapor deposition (LPCVD), as illustrated in FIG. 1B.
Then, as illustrated in FIG. 1C, both the silicon nitride film 607 and the polysilicon film 605 are patterned by a conventional process to thereby form a gate electrode 608 onto the gate oxide 604. As is obvious, the gate electrode 608 consists of the polysilicon film 605 and the silicon nitride film 607 deposited on the polysilicon film 605.
Then, as illustrated in FIG. 1D, arsenic (As) ions are implanted into the p-type silicon substrate 601 at opposite sides of the gate electrode 608 to thereby form diffusion layers 611 acting as source/drain regions.
Then, an insulating film composed of phosphorus silicate glass (PSG) or non-doped silicate glass (NSG) is deposited all over a resultant by normal pressure CVD, followed by anisotropic etching of the insulating film to thereby form a sidewall 609 around a sidewall of the gate electrode 608, as illustrated in FIG. 1E. Then, thermal annealing is carried out at 900.degree. C. for 30 minutes to thereby activate the source/drain regions 611.
Then, as illustrated in FIG. 1F, the silicon nitride film 607 deposited on the polysilicon film 605 is removed with heated phosphoric acid. Thus, the sidewall 609 projects above the gate electrode 608 now consisting of the polysilicon film 605.
Then, after the silicon substrate 601 has been washed with aqueous HF solution, a titanium (Ti) film is deposited all over a resultant, followed by lamp annealing in argon (Ar) gas at 600.degree. C. for 30 seconds. A portion of the titanium film being in direct contact with the polysilicon film 605 and the source/drain regions 611 is silicided by the lamp annealing, thereby there being formed a titanium silicide (TiSi.sub.2) film 614 covering the polysilicon film 605 and the source/drain regions 611, as illustrated in FIG. 1G. A portion of the titanium film located on the sidewall 609 and the field oxides 603 remains non-silicided. Then, the non-silicided portion of the titanium film is removed with mixture solution including ammonia, hydrogen peroxide and water.
Thereafter, a conventional process is carried out to complete a semiconductor device. In brief, an interlayer film such as a BPSG film is deposited over a resultant, followed by thermal treatment to carry out planarizing the BPSG film. Then, after a contact hole reaching the gate electrode has been formed, an aluminum film .including silicon therein at 1% is deposited, followed by patterning the aluminum film to thereby form a wiring.
In the above mentioned method, although an upper insulating film of the gate electrode 608 comprises a silicon nitride film, refractory nitride such as TiN and ZrN or refractory carbide such as TiC and ZrC may be used in place of the nitride film, in which case it is said in the Publication No. 3-288443 that mixture solution consisting of sulfuric acid and hydrogen peroxide may be used for removal of the upper insulating film of the gate electrode. It is also said that a is zirconium (Zr) film, a hafnium (Hf) film or a cobalt (Co) film may be used in place of a titanium film to be used as a metal film for the formation of a silicide film.
As mentioned earlier, the method includes the steps of forming a gate electrode having a two-layered structure, forming a sidewall around a sidewall of the gate electrode, and removing an upper insulating film of the gate electrode, to thereby cause the sidewall to project above the gate electrode now consisting of a lower layer or a polysilicon film. This structure suppresses horizontal growth of silicide while a silicide film is being deposited to thereby make it possible to prevent short-circuiting between a gate electrode and source/drain regions.
On the other hand, the inventors of the present invention have invented and filed the other method of projecting a sidewall above a polysilicon gate electrode in Japanese Patent Application No. 6-245740. Hereinbelow is explained the method with reference to FIGS. 2A to 2F which are cross-sectional views of a semiconductor fabrication method, showing respective step of the method. However, it should be noted that Japanese Patent Application No. 6-245740 is not yet published and does not constitute prior art to the present invention. The citation of the Application herein does not mean that the inventors admit the Application as prior art, and is done merely for better understanding of the present invention.
First, as illustrated in FIG. 2A, a plurality of field oxides 703 are formed by selective oxidation on a silicon substrate 701, followed by deposition of a gate oxide 704 in device formation region surrounded by the field oxides 703.
Then, as illustrated in FIG. 2B, there is deposited a polysilicon film 705 on the gate oxide 704, and subsequently a phosphorus silicate glass (PSG) film 707 is deposited on the polysilicon film 705 by 200 nanometers thickness by normal pressure chemical vapor deposition.
Then, as illustrated in FIG. 2C, the PSG film 707 and the polysilicon film 705 are successively, selectively etched for removal by photolithography and reactive ion etching (RIE). Thus, there is formed a gate electrode 708 consisting of the residual two films 707 and 705.
Then, as illustrated in FIG. 2D, at a sidewall of the gate electrode 708 is formed a sidewall 709 composed of silicon nitride by CVD and anisotropic etching. Then, impurities are ion-implanted into the silicon substrate 701 at opposite sides of the gate electrode 708 by using the field oxides 703, the two-layered gate electrode 708 and the sidewall 709 as a mask, to thereby form diffusion layers 711 acting as source/drain regions.
Then, as illustrated in FIG. 2E, the silicon substrate 701 is exposed to hydrofluoric anhydride vapor in a vacuum chamber to thereby selectively remove only an upper layer of the two-layered gate electrode 708, namely the PSG film 707. Thus, the sidewall 709 projects above an exposed surface of the polysilicon gate electrode 705 by 200 nanometers.
Then, as illustrated in FIG. 2F, there are selectively deposited tungsten (W) films 714 only on both the source/drain regions 711 and the polysilicon gate electrode 705 surrounded with the sidewall 709.
In the prior method having been explained with reference to FIGS. 1A to 1G, the silicon nitride film 607 is used as an upper insulating film of the gate electrode 608 in order to cause the sidewall 609 to project above the gate electrode 608 consisting only of the polysilicon film 605, and the silicon nitride film 607 is removed with heated phosphoric acid after the formation of the sidewall 609. In general, since PSG or NSG of which the sidewall 609 is composed has a low selectivity ratio to heated phosphoric acid, it is quite difficult to cause the sidewall 609 to project above the gate electrode 608 when the silicon nitride film 607 is to be removed with heated phosphoric acid. A general etching rate of a thermal oxide film when etched with heated phosphoric acid is about 0.1 nm/min, and hence the thermal oxide film is scarcely etched. However, an oxide film used in the prior method contains much of the impurities having been involved thereinto in ion-implantation, and is composed of PSG or NSG having lower formation temperature than a thermal oxide film, and hence the oxide film used in the prior method has an etching rate of about 4 nm/min in accordance with detailed inspection by the inventors. Thus, since the silicon nitride film 607 constituting an upper insulating film of the gate electrode 608 has an etching rate of about 10 nm/min, almost zero selectivity ratio is obtained.
In addition, a thickness of the sidewall has to become thinner as a more micro-sized semiconductor device is required. In particular, an upper end of the sidewall has a thinner thickness, and thus, the sidewall is isotropically etched in over-etching of the silicon nitride film, resulting in that it is difficult to cause the sidewall to project above the polysilicon gate electrode 608.
Furthermore, the diffusion layers 611 are also etched with heated phosphoric acid, resulting in that a surface of the silicon substrate 601 is made to be roughened.
In the case that an upper insulating layer of a two-layered gate electrode is to be composed of refractory nitride such as titanium nitride (TiN) and zirconium nitride or refractory carbide such as titanium carbide and zirconium carbide, there would arise a problem of contamination by metal caused by particles to be produced in the formation of the upper insulating layer or caused in subsequent ion-implantation and/or thermal annealing. Such contamination by metal causes many problems to arise in a salicidation process as follows: a silicide film is formed also on insulating films or field oxides, and hence a portion of an unreacted titanium film remains non-etched when the unreacted titanium film is to be etched; and the .selectivity is deteriorated in selective growth of a refractory metal film, thereby the refractory metal film being formed also on insulating films or field oxides with the result of deteriorated mass-productivity.
On the other hand, in the method having been explained with reference to FIGS. 2A to 2F, after the sidewall 709 has been formed by etching the polysilicon film 705 and the PSG film 707 into the two-layered gate electrode 708, only the PSG film 707 is etched for removal to thereby cause the sidewall 709 to project above the polysilicon film 705. Thus, the method of FIGS. 2A to 2F does not have such problems as found in the prior method of FIGS. 1A to 1G.
However, it has been found through studies having been made after the filing of Japanese Patent Application No. 6-245740 that the method suggested therein might cause other problems as follows. When a PSG film is to be selectively etched with hydrofluoric anhydride vapor, phosphoric acid (H.sub.3 PO.sub.4) is produced in liquid form out of the etched PSG film. The liquid phosphoric acid is easily dissolved in hydrofluoric acid (HF). Thus, since a silicon nitride film of which the sidewall 709 is composed has high wettability to phosphoric acid, the liquid phosphoric acid containing HF therein flows on the silicon nitride film, namely the sidewall 709, and may reach silicon regions in which the diffusion layers 611 are to be formed and further the field oxides 703 acting as device isolation regions. As a result, the field oxides 703 may be etched with HF dissolved in the liquid phosphoric acid. It is possible to selectively etch the PSG film 707 in the hydrofluoric anhydride vapor etching, because the field oxides 703 have a high selectivity ratio to the PSG film 707, whereas the field oxides 703 are etched together with the PSG film 707, because the field oxides have an increased etching rate in hydrofluoric acid dissolved in the liquid phosphoric acid. Since the field oxides 703 are etched in particular in the vicinity of the sidewall 709, the tungsten film 714 also .grows on an exposed surface of the silicon substrate 701 in subsequent silicidation step, resulting in that device isolation and junction leakage characteristic are degraded. If the reaction such as mentioned above further progresses, the gate oxide 704 is also etched with the result that it is almost impossible to fabricate a semiconductor device.